Design a Motor Control System

The Prompt

"Design a brushless DC motor controller with closed-loop speed control for an industrial fan. Requirements: 1000-10,000 RPM range, speed accuracy within 2%, CAN bus for setpoint commands, emergency stop input."

This is a classic embedded system design question that tests your ability to combine real-time control theory, power electronics awareness, ISR architecture, and safety thinking into a coherent design.

Requirements Clarification

Before sketching any architecture, clarify the requirements with the interviewer. Here is what a thorough requirements table looks like after the clarification phase:

Functional Requirements

Non-Functional Requirements

Architecture Overview

CAN Bus (500 kbps)
                            |
                            v
+-------+  +----------+  +-+----------+  +--------+  +-------+  +-------+
| Hall  |  | Encoder  |  |            |  | Gate   |  | 3-Ph  |  |       |
|Sensors+->+ / Speed  +->+    MCU     +->+Driver  +->+MOSFET +->+ BLDC  |
| (3x)  |  | Calc     |  |            |  | (Hi/Lo)|  |Bridge |  | Motor |
+-------+  +----------+  +-----+------+  +--------+  +-------+  +-------+
                            ^   ^   ^
                            |   |   |
                     +------+   |   +--------+
                     |          |            |
                +----+---+ +---+----+ +-----+-----+
                |Current | |Temp    | | E-Stop    |
                |Sense   | |Sensor  | | (HW latch)|
                |(2 ph)  | |(NTC)   | |           |
                +--------+ +--------+ +-----------+

Key architectural decisions visible in this diagram:

• Three Hall sensors for rotor position feedback (6-step commutation or FOC)
• Two-phase current sensing (third phase calculated by Kirchhoff's law: Ic = -Ia - Ib)
• Hardware E-stop path that disables the gate driver directly, independent of firmware
• Temperature monitoring on both the motor (NTC on winding) and the power stage (NTC on MOSFET heatsink)

Component Deep Dive

Position and Speed Sensing

Three approaches exist for BLDC rotor position sensing. The choice affects cost, complexity, and performance:

Decision for this design: Hall sensors. They meet the 2% speed accuracy requirement, work across the full RPM range including startup, cost less than a dollar total, and are standard in industrial BLDC fans. If the interviewer asks about higher precision, mention that adding an encoder enables FOC with better torque ripple performance.

Speed calculation from Hall sensors:

Speed (RPM) = 60 / (time_between_hall_edges * number_of_pole_pairs * 6)

Example: 7-pole-pair motor, hall edge every 714 us
  RPM = 60 / (714e-6 * 7 * 6) = 60 / 0.02999 = 2001 RPM

Use a timer capture on Hall edge interrupts to measure the period between edges. At 1000 RPM with 7 pole pairs, edges arrive every 1.43 ms — easily measurable with a 1 MHz timer.

Control Loop Architecture

The control system uses cascaded loops — an inner current loop for fast torque response and an outer speed loop for setpoint tracking:

Speed      +-------+   Current    +-------+   Duty    +-------+
  Setpoint ->+ Speed +-> Setpoint ->+Current+-> Cycle ->+  PWM  +-> Motor
       |     |  PID  |       |      |  PID  |     |     | Gen   |
       |     +---+---+       |      +---+---+     |     +-------+
       |         ^            |          ^         |
       |         |            |          |         |
       |    +----+----+       |     +----+----+    |
       +--->+ Speed   |       +---->+ Current |    |
            | Feedback|             | Feedback|    |
            +---------+             +---------+    |
            Hall/Encoder            ADC Shunt      |
                                                   |
                    20 kHz ISR handles all of this -+

Two control algorithm options:

Decision: Start with 6-step commutation — it is simpler to implement, well-proven for industrial fans, and meets the 2% speed accuracy requirement. Mention FOC as an upgrade path if the interviewer pushes for better performance.

PID tuning approach:

• Speed PID: proportional + integral (PI controller), loop rate 1 kHz (every 20th FOC cycle)
• Current PID: proportional + integral, loop rate 20 kHz (every PWM cycle)
• Anti-windup on integrator to prevent overshoot during setpoint changes
• Derivative term usually not needed for speed control (Hall quantization noise makes derivative noisy)

PWM Generation

Why center-aligned PWM matters:

Edge-aligned:
  ____                ____                ____
 |    |              |    |              |    |
_|    |______________|    |______________|    |___

Center-aligned:
       ____                ____
      |    |              |    |
 _____|    |______________|    |_____________
                  ^
                  |
          Best ADC sampling point
          (current is most stable here)

Center-aligned PWM creates a symmetrical switching pattern. The midpoint of the ON period is the ideal time to sample phase currents because switching transients have settled.

Safety System

Safety is not optional in motor control. The interviewer expects you to discuss these failure modes:

Critical safety design principle: The E-stop and overcurrent protection must have a hardware path that disables the gate driver without firmware involvement. If the MCU firmware hangs, the hardware safety path still functions.

E-Stop Pin (Active Low)
       |
       v
 +-----+------+
 |  Gate       |     Firmware cannot override
 |  Driver     +---> this hardware shutdown path
 |  ENABLE pin |
 +---------+---+
            ^
            |
 Overcurrent Comparator Output

Communication

CAN message format example:

MCU Selection

Decision: STM32G474. It has integrated analog comparators for hardware overcurrent protection, advanced timers with center-aligned PWM and dead-time insertion, multiple ADCs for simultaneous current sampling, and CAN-FD. The Cortex-M4 FPU handles PID math in single-precision float without performance penalty. The price fits the $25 BOM target.

Key Design Decisions Summary

Timing Analysis

This is where you demonstrate that the design actually works within real-time constraints.

ISR Budget at 20 kHz (50 us period)

Margin: 42.4 us remaining per cycle. This leaves substantial headroom for:

• Future FOC upgrade (Clarke + Park transforms add approximately 5 us)
• Additional safety checks within the ISR
• Worst-case interrupt latency from lower-priority tasks

Task Timing (Non-ISR)

Total CPU utilization: approximately 16% — well within safe operating margin. The industry guideline is to keep utilization under 70% to allow for worst-case jitter and future growth.

Memory Budget

What Interviewers Evaluate

Real-time thinking: Can you calculate an ISR budget and explain why 20 kHz is the right control loop frequency? Can you explain what happens if the ISR overruns its period?

Safety-first design: Did you discuss overcurrent protection before the interviewer asked? Did you put the E-stop on a hardware path instead of a GPIO polled in firmware?

Concrete numbers: "The PID runs in 3 us" is stronger than "the PID is fast enough." Interviewers want to see that you can estimate cycle counts and timing budgets.

Tradeoff awareness: Explaining why you chose 6-step over FOC (simpler, sufficient for this application, upgrade path exists) is more impressive than just picking FOC because it is more advanced.

System-level perspective: The motor controller does not exist in isolation. You should mention the CAN network, the host controller sending setpoints, electromagnetic compatibility of the switching stage, and thermal management of the power MOSFETs.

Knowing what you do not know: It is perfectly fine to say "I would consult the motor datasheet for the torque constant and back-EMF coefficient before finalizing the current limits" rather than inventing numbers.