Compare JTAG and SWD for debugging embedded systems. When would you choose one over the other?

JTAG (Joint Test Action Group, IEEE 1149.1) is the original debug and boundary-scan interface. It uses at minimum four signals: TCK (clock), TMS (mode select), TDI (data in), and TDO (data out), plus an optional TRST (reset). JTAG supports daisy-chaining multiple devices on a single scan chain, which is essential for debugging complex boards with multiple ICs (MCU + FPGA + DSP). It also supports boundary scan testing — the ability to toggle and read individual pins of a device without running any code — making it invaluable for board-level manufacturing test and verifying solder connections.

SWD (Serial Wire Debug) is an ARM-specific two-pin debug protocol that uses SWDIO (bidirectional data) and SWCLK (clock). It provides the same CoreSight debug functionality as JTAG on ARM Cortex-M and Cortex-A cores — breakpoints, watchpoints, register inspection, flash programming, and real-time memory access — but with only two pins instead of four or five. SWD also supports the SWO (Serial Wire Output) pin for trace output (ITM stimulus ports), which JTAG does not natively provide.

Choose SWD for the vast majority of ARM Cortex-M projects: it uses fewer pins (critical on small QFN packages where every pin is precious), achieves the same debug speeds, and the SWO trace capability is a significant bonus. Choose JTAG when you need to debug non-ARM devices (MIPS, RISC-V, FPGAs), when you need boundary scan for production testing, or when you have a multi-device scan chain. On boards with both an ARM MCU and an FPGA, a common setup is to use the JTAG scan chain for the FPGA and break out a separate SWD header for the ARM core.