Search topics...
Memory Technologies & Systemsfoundational

Conceptually, what do you need to do after reconfiguring a digital PLL? What if the digital PLL sources the clock for your microcontroller (and other concerns)?

0 upvotes
Practice with AISoon

After reconfiguring any PLL: changing the PLL's multiplier/divider/reference takes it out of lock. You must wait for the PLL to re-lock (poll the PLL lock-status bit, or wait the datasheet-specified lock time) before using its output, otherwise downstream logic is clocked by an unstable, jittery, possibly out-of-spec clock.

If the PLL sources the CPU/system clock, you cannot simply reprogram it while running from it — you'd be sawing off the branch you're sitting on. The safe sequence is:

  1. Switch the CPU/system clock source to a safe, stable clock first — typically the internal RC oscillator or the raw crystal — so the core keeps running while the PLL is down.
  2. Reconfigure the PLL (new multiplier/dividers/reference).
  3. Wait for PLL lock (poll the lock bit).
  4. Adjust settings that depend on the new (usually higher) frequency before switching back:
    • Increase Flash wait-states / read-access latency to match the faster clock (running Flash too fast without enough wait states corrupts instruction fetches).
    • Raise core voltage / select the correct power/performance mode if the higher frequency requires it (and configure any prefetch/accelerator).
  5. Switch the CPU clock source back to the PLL output.
  6. Reconfigure dependent peripheral clock dividers so peripherals stay in spec: UART/USART baud-rate generators, SPI/I²C clocks, timer prescalers, PWM, ADC clocks, watchdog, SysTick, USB (needs a precise 48 MHz), etc. Any peripheral whose timing was derived from the old frequency must be recomputed.

Other concerns: lock-time/jitter tolerance of consumers; glitch-free clock-switch hardware (use the MCU's clock-switch mux, don't gate manually); the reverse path when lowering frequency (switch source first, then you may reduce wait states/voltage afterward); ensuring you don't exceed any intermediate bus (AHB/APB) max frequency during the transition; and re-validating real-time deadlines and any baud/timer values cached in software.