Explain the trade-off between PWM frequency and duty cycle resolution.

Both frequency and resolution are constrained by the timer clock. The duty cycle has (ARR + 1) discrete steps, and the minimum duty cycle increment is 1 / (ARR + 1). Higher PWM frequency requires a smaller ARR value (since f_PWM = f_CLK / ((PSC + 1) * (ARR + 1))), which directly reduces the number of available duty cycle steps. This is a fundamental hardware constraint that cannot be avoided — you are distributing a fixed number of timer clock ticks between frequency and resolution.

Consider a concrete example with a 72 MHz timer clock and PSC = 0: at 1 kHz PWM, ARR = 71999, giving 72000 duty cycle steps (approximately 16.1 bits of resolution). At 100 kHz, ARR = 719, giving only 720 steps (approximately 9.5 bits). At 1 MHz, ARR = 71, giving just 72 steps (approximately 6.2 bits). For a motor controller that needs 10-bit resolution (1024 steps) at 20 kHz, the required timer clock is at least 20,000 * 1024 = 20.48 MHz — easily achievable with any modern MCU.

When the application demands both high frequency and fine resolution beyond what the timer clock supports, the solutions are: (1) use a faster timer clock if the MCU permits it, (2) use dithering — alternate between adjacent duty cycle values across multiple PWM periods so the time-averaged duty cycle has higher effective resolution than any single period, or (3) use a dedicated PWM controller IC with higher bit-depth counters (some motor control ICs have 300+ MHz counter clocks).