Explain UART, SPI, I2C buses. Describe some of the signals in each. At a high-level describe each. Have you ever used any? Where? How? What type of test equipment would you want to use to debug these types of buses? Have you ever used test equipment to do it? Which?

These are the three workhorse serial buses found on virtually every embedded board. They differ along three axes: synchronous vs. asynchronous, number of wires, and addressing/topology.

UART (Universal Asynchronous Receiver/Transmitter)

• Asynchronous: there is no shared clock line. Both ends must be pre-configured to the same baud rate (e.g., 9600, 115200), and they recover timing from the data stream itself.
• Signals: TX (transmit) and RX (receive) — note these cross over between the two devices (one's TX goes to the other's RX). Optional hardware flow control adds RTS/CTS (Request To Send / Clear To Send). Ground must be common.
• Framing: each character is sent as a frame consisting of a start bit (logic 0), 5–9 data bits (typically 8, LSB-first), an optional parity bit (even/odd for simple error detection), and 1, 1.5, or 2 stop bits (logic 1). The classic shorthand is "8N1" = 8 data bits, no parity, 1 stop bit.
• Topology: point-to-point, full-duplex. No master/slave concept; both sides are peers.
• Use: console/debug logging, GPS modules, modems, sensor modules, board-to-board links. Often exposed via a USB-to-serial bridge (FTDI/CP210x/CH340) at 3.3 V or 5 V logic levels (not RS-232 voltages unless a transceiver like a MAX232 is added).

SPI (Serial Peripheral Interface)

• Synchronous, full-duplex, master/slave (controller/peripheral) bus driven by the master's clock.
• Signals: SCLK (serial clock from master), MOSI/COPI (Master Out Slave In / Controller Out Peripheral In), MISO/CIPO (Master In Slave Out / Controller In Peripheral Out), and CS/SS (Chip Select / Slave Select, usually active low). Each additional slave needs its own dedicated CS line.
• Modes: four combinations of clock polarity and phase — CPOL (idle clock level) and CPHA (which clock edge samples data) define modes 0–3. Master and slave must agree on the mode.
• Characteristics: very fast (tens of MHz), no built-in addressing or acknowledgment, no flow control. Simple shift-register hardware on both ends; data shifts out MOSI while it simultaneously shifts in on MISO.
• Use: high-speed peripherals — SPI flash/EEPROM, SD cards (SPI mode), displays (TFT/OLED), ADCs/DACs, radios.

I2C (Inter-Integrated Circuit, "I-squared-C")

• Synchronous, two-wire, multi-drop bus shared by all devices.
• Signals: SDA (serial data) and SCL (serial clock). Both lines are open-drain/open-collector and require external pull-up resistors to Vcc; devices only pull low, never drive high.
• Addressing: each slave has a 7-bit address (10-bit addressing also exists), so many devices share the same two wires.
• Protocol: the master issues a START condition (SDA falling while SCL high), sends address + R/W bit, and each byte is followed by an ACK/NACK from the receiver. A STOP condition (SDA rising while SCL high) ends the transaction. Clock stretching lets a slow slave hold SCL low to pause the master. The bus supports multi-master arbitration via the wired-AND nature of open-drain (a master that loses arbitration backs off).
• Speeds: standard 100 kHz, fast 400 kHz, fast-mode-plus 1 MHz, high-speed 3.4 MHz.
• Use: low-speed configuration and sensor traffic — IMUs, temperature/humidity sensors, EEPROMs, RTCs, power-management ICs, HDMI EDID.

Test equipment to debug these buses (technical core):

• Logic analyzer is the primary tool. A multi-channel logic analyzer (e.g., Saleae, or a benchtop unit) with protocol decoders for UART/SPI/I2C is ideal — it shows the digital bit stream and decodes it into bytes, addresses, ACK/NACK, and start/stop conditions. This is the fastest way to confirm framing, baud, mode, and addressing.
• Oscilloscope for the analog/electrical view: signal integrity, rise/fall times (especially I2C pull-up sizing and bus capacitance), voltage levels, ringing, and glitches. Many modern scopes have serial decode options too (mixed-signal oscilloscopes combine scope channels with logic channels).
• Dedicated protocol/bus analyzers for harder problems or compliance testing.
• Practical debugging checks: for UART, verify baud/parity/stop bits and TX↔RX crossover; for SPI, verify the CPOL/CPHA mode and CS timing; for I2C, verify pull-ups are present and correctly sized, watch for missing ACKs (wrong address or absent device), and check for clock stretching or a stuck-low bus.

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