Have you ever written code to initialize (configure) low-power self-refreshing DRAM memory after power up (independent of BIOS or other code that did it for the system)?

Bringing up DRAM (SDRAM/DDR/LPDDR) from scratch means programming the memory controller and running the JEDEC-defined device init sequence, because at reset the controller and DRAM are uninitialized and DRAM contents are invalid. Conceptually:

1. Configure the memory controller timing parameters to match the specific DRAM part's datasheet: tRCD (RAS-to-CAS delay), tRP (precharge), tRAS (row active time), tRC, tRFC (refresh cycle), tWR, CAS latency (CL), burst length, and the bus width / row-column-bank addressing geometry. Also configure the I/O (drive strength, ODT) and, for DDR, the DLL/PLL and read/write DQS timing or training/calibration.
2. Apply clocks and wait the required power-up stabilization time (e.g., ≥100 µs / 200 µs with stable clock, per JEDEC) before issuing commands.
3. Run the device initialization command sequence:
   • Issue Precharge All banks.
   • Load Mode Register(s): program the Mode Register (MRS) with CAS latency, burst length, burst type; and Extended Mode Register(s) (EMRS) for DDR/LPDDR features (DLL enable, drive strength, self-refresh/temperature-compensated self-refresh options).
   • Issue the required number of auto-refresh cycles (typically two or more) to stabilize the sense amps.
   • For DDR, reset and wait for the DLL to lock, and perform read/write leveling/training as required.
4. Program the refresh interval / refresh counter so the controller issues auto-refresh within tREF (e.g., one refresh per row every 64 ms).
5. Enable the controller for normal operation (and only then is the array usable).

For low-power self-refresh: the controller hands off refresh responsibility to the DRAM's internal refresh oscillator during low-power/standby. Software (or the controller hardware) performs the self-refresh entry handshake (e.g., assert the self-refresh entry command/condition, stop the external clock as allowed) before sleeping, and the exit handshake on wake (restart clock, wait the required tXSR stabilization time, re-enable controller-driven auto-refresh, possibly re-train DDR timing) before issuing the first normal access. LPDDR adds features like partial-array self-refresh (PASR) and temperature-compensated self-refresh (TCSR) to cut refresh power. The whole sequence is part-specific — you must follow the exact device datasheet and JEDEC spec.