How do circular buffers with Half-Transfer (HT) and Transfer-Complete (TC) interrupts work?

In circular DMA mode, the DMA controller continuously transfers data between a peripheral and a memory buffer, automatically wrapping the memory pointer back to the beginning when it reaches the end. This creates an infinite ring buffer that operates without any CPU intervention to restart or reconfigure transfers. The hardware maintains the write position internally via the NDTR (Number of Data to Transfer Register), which decrements with each transfer and reloads to the full buffer size on wrap-around.

The buffer is logically divided into two halves, and the DMA controller generates two interrupts per complete cycle. The Half-Transfer (HT) interrupt fires when the DMA has filled the first half of the buffer and begins writing to the second half. The Transfer-Complete (TC) interrupt fires when the second half is full and the DMA wraps back to the buffer start. This creates a natural ping-pong double-buffering scheme: when HT fires, the CPU processes the first half while DMA fills the second; when TC fires, the CPU processes the second half while DMA fills the first. The CPU always has a full half-buffer's worth of time to complete processing before DMA overwrites the data.

// Circular DMA double-buffering pattern
#define BUF_SIZE 256
uint16_t adc_buf[BUF_SIZE];

void DMA1_Channel1_IRQHandler(void) {
    if (DMA1->ISR & DMA_ISR_HTIF1) {
        DMA1->IFCR = DMA_IFCR_CHTIF1;
        process(adc_buf, BUF_SIZE / 2);           // First half
    }
    if (DMA1->ISR & DMA_ISR_TCIF1) {
        DMA1->IFCR = DMA_IFCR_CTCIF1;
        process(adc_buf + BUF_SIZE / 2, BUF_SIZE / 2); // Second half
    }
}

This pattern is the backbone of real-time audio processing, continuous ADC sampling, and high-throughput UART/SPI reception. The buffer size must be chosen so that the worst-case CPU processing time for one half is less than the time DMA takes to fill the other half. If processing overruns, data is silently corrupted — there is no hardware protection, no error flag, and no interrupt. Sizing the buffer correctly requires knowing both the data arrival rate and the worst-case processing time.