How do you determine the maximum SPI clock speed for a given system?

The maximum achievable SPI clock speed is the minimum of several independent constraints, and finding it requires checking each one:

Slave device limit. The datasheet specifies the maximum SCK frequency the slave supports — often as a function of supply voltage (e.g., 20 MHz at 3.3V, 10 MHz at 1.8V). This is the absolute ceiling.

Master peripheral prescaler. The MCU's SPI peripheral divides the APB clock by a power-of-two prescaler (2, 4, 8, 16, ...). If the APB clock is 72 MHz, the available SPI clock rates are 36, 18, 9, 4.5 MHz, etc. You must choose the highest prescaler setting that keeps the SPI clock at or below the slave's maximum.

PCB trace length and capacitance. Longer traces and higher capacitance slow edge rates and increase propagation delay. A rule of thumb: if the round-trip propagation delay (master to slave and back) exceeds 25% of the clock period, setup/hold time violations are likely. For a 10 cm trace on FR4 (delay ~0.5 ns/cm), the round-trip is about 10 ns — fine for 10 MHz (100 ns period) but marginal for 50 MHz (20 ns period).

Level shifters in the signal path. Bidirectional level shifters (like TXB0104) add 2-10 ns of propagation delay per direction. At high SPI speeds, this delay can violate timing. Dedicated unidirectional level shifters (74LVC series) are faster but require separate components for each direction.

Setup and hold time margins. Even if the slave's maximum frequency is 20 MHz, the actual achievable speed depends on whether the master's output-to-valid delay plus trace propagation delay leaves enough margin for the slave's setup time. Conservative designs run at 50-75% of the theoretical maximum to provide margin.