How does chip select (CS) work, and what are the timing requirements around it?

Chip select is a dedicated active-low signal from the master to each slave. When CS is driven low, the slave is selected: it enables its MISO output driver and begins responding to clock transitions. When CS is high, the slave ignores SCK and MOSI, and its MISO output enters high-impedance (tri-state) to avoid bus contention.

Timing around CS is critical and often overlooked. Most SPI slave devices specify two timing parameters in their datasheets: (1) CS setup time — the minimum time CS must be asserted (low) before the first SCK edge, typically 5-50 ns. If you violate this, the slave is not ready and misses the first bit. (2) CS hold time — the minimum time CS must remain asserted after the last SCK edge, before being de-asserted. Violating this can cause the slave to discard the last byte.

Additionally, many devices require a minimum CS high time between transactions — the time CS must remain de-asserted before it can be asserted again. Flash memories, for example, often need 50-100 ns of CS high time to latch the previous command. At SPI clock speeds above 10 MHz, firmware that de-asserts and immediately re-asserts CS may violate this timing. Inserting a few NOPs or using a GPIO toggle with a brief delay between transactions solves this.

When using hardware-managed CS (where the SPI peripheral controls the CS pin automatically), verify that the peripheral's behavior matches the slave's requirements. Some MCU SPI peripherals de-assert CS between every byte by default, which breaks multi-byte transactions for slaves that expect CS to remain low for the entire command sequence. In such cases, use software-controlled CS (a regular GPIO pin) for more precise control.