How does SPI daisy-chaining work, and what are its trade-offs?

In daisy-chain topology, all slaves share a single CS line. The MISO output of the first slave connects to the MOSI input of the second slave, and so on, forming a serial shift-register chain. The master's MOSI connects to the first slave's input, and the last slave's MISO connects back to the master's MISO input.

To communicate, the master must clock out N x word_size bits, where N is the number of slaves in the chain. Data shifts through each slave sequentially: the first word clocked out reaches the last slave, and the last word stays in the first slave. All slaves latch their data simultaneously on the CS rising edge.

The primary advantage is pin savings — only one CS line is needed regardless of the number of slaves. This is particularly valuable for LED driver chains (like WS2812 or APA102 strings), shift-register cascades, and DAC chains where many identical devices are connected. The disadvantages are significant: (1) increased latency — you cannot address a single slave without clocking through the entire chain; (2) increased transaction length — every communication involves all slaves, even if only one needs updating; (3) single point of failure — if any slave in the chain fails, all downstream devices become unreachable; (4) no readback from specific devices — the data that comes back on MISO is a concatenation of all slaves' outputs, shifted by the chain position.

Daisy-chaining is appropriate when all devices are identical and updated together (LED arrays, shift register chains) but poor for mixed peripherals where you need to address individual devices independently.