In which direction does the stack grow in various processor families?

Stack growth direction is whether push moves the stack pointer toward lower or higher addresses. On essentially all mainstream architectures the stack grows down (toward lower addresses), with the stack typically placed at the top of RAM growing down toward the heap, which grows up.

• x86 / x86-64: Grows down. push decrements ESP/RSP; call pushes the return address downward.
• ARM (Cortex-M and most ARM software, AAPCS/EABI): Grows down ("full descending" stack is the standard convention — SP points at the last pushed item and pre-decrements on push). The ARM architecture technically supports other stack models (full/empty, ascending/descending via STM/LDM addressing modes), but the EABI/AAPCS used everywhere is full descending, i.e., down. On Cortex-M, exception entry hardware-stacks downward as well.
• RISC-V: Grows down by convention (the ABI uses a full-descending stack; sp is decremented to allocate a frame).
• AVR (ATmega / Arduino): Grows down — push post-decrements the SP register; the stack is placed at the top of SRAM and grows toward lower addresses.
• MIPS, SPARC, PowerPC, 68k: Grow down by convention as well.

The accurate nuance: stack-growth direction is largely a software/ABI convention enforced by the calling convention, not always a hard CPU mandate. A few architectures or configurations grow up (toward higher addresses) — for example, certain conventions on PA-RISC historically used an upward-growing stack, and some specialized/embedded toolchains can be configured for ascending stacks. So the precise answer is: "almost universally down on x86, ARM EABI, and RISC-V, but it's ultimately set by the ABI, and a handful of architectures grow up."

Why it matters in embedded: stack overflow grows into whatever is adjacent (often the heap or .bss), so knowing the direction tells you where corruption appears and where to place guard regions / MPU stack-limit protection (e.g., Cortex-M PSPLIM/MSPLIM).