What happens if the baud rates of two UART devices do not match?

If baud rates differ by more than about 3-5%, the receiving UART samples bits at the wrong points within each bit period, producing garbled data. The receiver uses the falling edge of the start bit to synchronize, then samples each subsequent bit at the center of its expected time window. As the frame progresses, timing error accumulates. By the time the receiver reaches the stop bit (bit 9 or 10), the cumulative drift may have shifted the sample point into the adjacent bit, causing framing errors and corrupted data.

The tolerance is tighter than many engineers expect. At 8N1, the receiver must correctly sample 10 consecutive bits. If the baud rate error is 5%, the sample point drifts by 0.5 bit periods over 10 bits — right at the boundary of the next bit. In practice, 2-3% is the safe limit, and you should aim for under 1%.

This is particularly important when deriving the baud rate from the MCU system clock. The UART baud rate generator divides the peripheral clock by an integer (or fractional) divisor. If the peripheral clock does not divide evenly into the target baud rate, there is an inherent error. For example, generating 115200 baud from a 8 MHz clock gives a divisor of 69.44 — rounding to 69 produces a 0.64% error. But generating 9600 baud from an 11.0592 MHz crystal gives an exact divisor of 1152, producing zero error. This is why 11.0592 MHz crystals were historically popular in UART-heavy designs.