What is clock gating and why does it matter?

Clock gating is the practice of disabling the clock signal to unused peripheral blocks so their internal flip-flops stop toggling and consume zero dynamic power. On STM32, every peripheral has an individual clock enable bit in the RCC (Reset and Clock Control) registers — for example, RCC->APB1ENR |= RCC_APB1ENR_USART2EN enables USART2's clock, and clearing that bit disables it. After reset, most peripheral clocks are disabled by default. Dynamic power in CMOS circuits is proportional to P = C * V^2 * f — by stopping the clock (f = 0), the dynamic power consumption of that peripheral block drops to essentially zero (only static leakage remains).

Clock gating is the simplest and most effective power optimization available to the embedded engineer, yet it is frequently overlooked. A typical STM32F4 application might enable clocks for GPIOA-E, USART1, SPI1, I2C1, TIM2, and DMA1 — but leave clocks enabled for DMA2, TIM3-TIM14, USART2-6, ADC1-3, and other unused peripherals that the HAL or BSP initialization code enabled "just in case." Each unused peripheral with an active clock wastes hundreds of microamps to several milliamps, depending on the peripheral complexity and the clock frequency. In a battery-powered design where the power budget is 50 mA active and 10 uA sleep, leaving unnecessary peripheral clocks running can waste 10-20% of the active power budget for zero benefit.

Best practices: (1) only enable peripheral clocks immediately before configuring the peripheral, and disable them when the peripheral is no longer needed (e.g., disable USART clock after a transmission is complete if communication is bursty); (2) audit your RCC enable register values — print them during development to identify unnecessarily enabled clocks; (3) use the MCU's power consumption calculator (STM32CubeMX has one) to estimate per-peripheral current draw; (4) during low-power mode entry, disable all peripheral clocks except those needed for wake-up detection. Clock gating has zero impact on functionality (a disabled peripheral simply freezes in its current state and its registers retain their values on most STM32 families) and zero code complexity — it is essentially free power savings.