What is dead-time insertion, and why is it critical for motor control?

Dead-time insertion adds a brief delay between turning off one transistor in a half-bridge and turning on the complementary transistor on the opposite side. This delay is necessary because power MOSFETs and IGBTs do not turn off instantaneously — the gate charge must be removed and the current through the device must fall to zero, a process that takes tens to hundreds of nanoseconds depending on the device. If the complementary transistor turns on before the first one has fully turned off, both transistors conduct simultaneously, creating a direct short circuit from the power rail to ground. This shoot-through event causes massive current spikes (potentially hundreds of amps for microseconds) that can destroy both FETs instantly, damage the gate drivers, and create severe EMI events.

On STM32, the advanced timers (TIM1, TIM8) provide complementary output channel pairs (CHx and CHxN) with a hardware dead-time generator controlled by the DTG field in the BDTR (Break and Dead-Time Register). The dead-time duration is specified in timer clock ticks and typically ranges from 100 ns to 2 us, depending on the FET switching characteristics. The DTG field uses a non-linear encoding that provides fine resolution at short dead-times and coarser steps at longer values. The dead-time must be longer than the worst-case turn-off time of the transistor (including driver propagation delay) but short enough to avoid excessive output waveform distortion.

A critical safety point: never implement dead-time in software alone. Software dead-time relies on CPU timing between writing two GPIO pins, which is vulnerable to interrupt latency — a single ill-timed interrupt could eliminate the dead-time entirely, causing shoot-through. The hardware dead-time generator in the timer operates independently of the CPU and guarantees the minimum dead-time under all conditions. The BDTR register also includes a break input (BRK) that immediately forces all outputs to a safe state (high-impedance or predetermined level) in response to an external fault signal — such as an over-current detector.