What is NOR-Flash and NAND-Flash memory? Are there any unique software concerns for either?

Both are non-volatile, electrically-erasable, block-erased Flash, but their cell array organization gives them very different characteristics and use cases.

NOR Flash:

• Cells arranged so each is individually addressable, giving full random read access with an address/data bus like RAM.
• Fast reads, and supports Execute-In-Place (XIP) — the CPU can fetch and run code directly from NOR without copying it to RAM. Ideal for boot code and firmware storage.
• Slow, energy-expensive erase and (relatively) slow writes; lower density and higher cost per bit.
• Typically no bad blocks from the factory and high read reliability; usually doesn't require ECC.
• Software concerns: erase granularity (sector/block) and erase-before-write still apply; mostly used for code and small read-mostly data.

NAND Flash:

• Cells arranged in series strings, accessed by page (read/program) and erased by block — there is no true random byte read; you read/write whole pages.
• High density, low cost per bit, faster program and erase than NOR — ideal for mass storage (SSDs, eMMC, SD cards, large data/file storage).
• Cannot reliably XIP; code must be copied (shadowed) into RAM to execute.
• Requires ECC — NAND bits flip (read/program disturb, retention) so an error-correcting code must protect each page.
• Bad-block management is mandatory — NAND ships with factory bad blocks and develops more over life; software/controller must maintain a bad-block table and remap.
• Generally needs a Flash Translation Layer (FTL) and wear leveling, often a log-structured/journaling filesystem (e.g., YAFFS2, UBIFS, JFFS2) or a managed-NAND controller (eMMC/UFS) that hides all this.

Summary of unique software concerns: NOR → leverage XIP, treat as code/read-mostly memory, handle sector erase. NAND → page-oriented access, mandatory ECC, bad-block remapping, wear leveling, and an FTL/flash filesystem; code must be shadowed to RAM. Both → erase-before-write, endurance limits, and power-fail-safe update strategies.