What is RISC-V? What is it's claimed pros or cons?

RISC-V is an open, royalty-free instruction set architecture (ISA) originally developed at UC Berkeley and now stewarded by RISC-V International. It is a load/store RISC design defined as a small base integer ISA (RV32I / RV64I / RV128I, plus RV32E for embedded with fewer registers) extended by optional standard extensions, each denoted by a letter: M (integer multiply/divide), A (atomics), F/D/Q (floating point), C (compressed 16-bit instructions), V (vector), B (bit-manipulation), etc. The popular general-purpose combination is abbreviated G, which is IMAFD plus the Zicsr (control/status-register) and Zifencei (instruction-fetch fence) extensions. It also defines privilege levels (machine/supervisor/user) for everything from microcontrollers to Linux-capable application processors.

It is an ISA specification, not a specific chip — anyone can design, fabricate, or license cores that implement it (open-source cores like Rocket, BOOM, and commercial ones from SiFive, Andes, etc.).

Claimed pros

• Open and royalty-free: No per-core licensing fees or architectural license required (unlike ARM or x86). Lowers cost and barrier to entry; appealing for academia, startups, and nations/companies seeking supply-chain independence.
• Modular / extensible: You include only the extensions you need — a tiny RV32EC microcontroller or a full RV64GC Linux core. Clean, lean base ISA.
• Custom extensions: Reserved opcode space lets designers add domain-specific custom instructions (accelerators, DSP, ML) legally and standardly — strong for specialized SoCs.
• Clean-slate design: Learned from prior ISAs; orthogonal, simple, no legacy baggage; good for teaching and for compiler/tooling clarity.
• Growing ecosystem: GCC/LLVM, Linux, FreeRTOS/Zephyr, and broad industry backing.

Claimed cons

• Ecosystem maturity vs. ARM/x86: Toolchains, debuggers, middleware, and especially a deep base of validated production software and third-party IP are less mature than ARM's decades-old ecosystem.
• Fragmentation risk: The very extensibility that's a pro can cause incompatible custom extensions and many ISA permutations, complicating binary portability and software support ("which extensions does this chip actually have?").
• Performance/maturity of available cores: High-performance, well-verified RISC-V application cores are catching up but historically trailed top-tier ARM/x86 designs; physical IP, optimized libraries, and silicon-proven high-end cores are fewer.
• "Open ISA" ≠ "open chip": Commercial RISC-V cores can still be proprietary and licensed; openness is at the ISA spec level.
• Less standardized platform layer: Boot, firmware, and platform conventions are still consolidating compared to the mature ARM SystemReady / x86 PC platform standards.
• Verification/validation burden falls more on implementers given the freedom to customize.