What is SPI and what are its main advantages over I2C and UART?

SPI (Serial Peripheral Interface) is a synchronous, full-duplex serial protocol with a master-slave architecture using four signals: SCK (clock), MOSI (Master Out Slave In), MISO (Master In Slave Out), and CS/SS (Chip Select). The master generates the clock and selects which slave to communicate with by asserting its chip select line.

SPI's primary advantages stem from its simplicity and speed. (1) High throughput — SPI clock rates commonly reach 10-50 MHz, with some devices supporting 100+ MHz. There is no addressing overhead, no ACK/NACK handshaking, and no start/stop bit framing — every clock cycle transfers one bit of useful data in each direction. (2) Full duplex — MOSI and MISO operate simultaneously, so the master sends a command while receiving the response to the previous command. This pipelining doubles effective throughput for protocols that exploit it. (3) Simple hardware — at its core, SPI is just two shift registers connected in a ring. A slave can be implemented with a single shift register IC and a few gates, making it trivial to bit-bang in software.

The cost of this simplicity is that SPI has no built-in error detection (no ACK, CRC, or parity), no standard for multi-master operation, and requires one dedicated CS pin per slave — which becomes a real constraint when connecting many peripherals.