What is the difference between a hardware interrupt and a software interrupt?

A hardware interrupt (also called an external interrupt) is triggered by a peripheral or external signal — for example, a GPIO pin changing state, a UART receiving a byte, a timer reaching its compare value, or a DMA transfer completing. Hardware interrupts are asynchronous to the program's execution and can occur at any time.

A software interrupt is triggered deliberately by executing a special instruction (e.g., SVC on ARM, INT on x86). In embedded RTOS systems, software interrupts are commonly used for system calls — when a task needs to request a kernel service (e.g., create a task, send to a queue), it executes an SVC instruction, which traps into the kernel in a controlled way. This mechanism provides a clear boundary between user code and kernel code.

On ARM Cortex-M, the NVIC (Nested Vectored Interrupt Controller) manages interrupt priorities and nesting. Interrupts can be maskable (can be disabled via the interrupt enable bit or PRIMASK/BASEPRI registers) or non-maskable (NMI — cannot be disabled and is reserved for critical faults like clock failures). An interview may ask about interrupt nesting: on Cortex-M, a higher-priority interrupt can preempt a lower-priority ISR, and the hardware handles the register saving automatically. The priority level is set via the NVIC priority registers, and on Cortex-M, lower numeric priority values mean higher urgency.