What is the PLL and how do you calculate its output frequency?

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Accepted Answer

The PLL (Phase-Locked Loop) is a clock multiplier circuit that takes a low-frequency input clock and generates a much higher-frequency output. On STM32F4, the main PLL has four programmable dividers/multipliers that form a frequency synthesis chain. The input source is either HSI (16 MHz) or HSE (typically 8 or 25 MHz), selected by the PLLSRC bit. The chain is:

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VCO_input  = PLL_source / M     (must be 1-2 MHz, typically 1 MHz)
VCO_output = VCO_input  * N     (must be 100-432 MHz)
SYSCLK     = VCO_output / P     (the main system clock)
USB_CLK    = VCO_output / Q     (must be exactly 48 MHz for USB)

The VCO (Voltage-Controlled Oscillator) is the core of the PLL and must operate within its valid frequency range (100-432 MHz on STM32F4). If VCO_output is configured outside this range, the PLL will not lock — meaning it either oscillates at an unpredictable frequency or fails to stabilize at all, which produces a clock that jitters wildly and causes intermittent hard faults or peripheral misbehavior. The M divider scales the input down to the VCO's input range (1-2 MHz recommended for best jitter performance), and N multiplies it up to the target VCO frequency. P divides the VCO output to produce SYSCLK, and Q divides it to produce the 48 MHz USB clock.

For a concrete example with an 8 MHz HSE crystal targeting 168 MHz SYSCLK and 48 MHz USB: M = 8 gives VCO_input = 1 MHz; N = 336 gives VCO_output = 336 MHz (within the 100-432 MHz range); P = 2 gives SYSCLK = 168 MHz; Q = 7 gives USB_CLK = 48 MHz. A common mistake is choosing N and P values that produce the correct SYSCLK but push VCO_output outside the valid range — for example, M = 4, N = 84, P = 1 gives SYSCLK = 168 MHz but VCO_output = 168 MHz * 1 = only 168 MHz, which is within range but leaves no headroom. Or choosing values where VCO_output/Q does not produce exactly 48 MHz, silently breaking USB. Some STM32 families (H7) have additional PLL outputs (PLL1P, PLL1Q, PLL1R) and fractional-N dividers for even finer frequency control.