What is VTOR and when would you relocate the vector table?

The Vector Table Offset Register (VTOR) is a system control register (at address 0xE000ED08 on Cortex-M3/M4/M7) that tells the processor where to find the vector table in memory. After reset, VTOR defaults to 0x00000000, meaning the processor fetches exception and interrupt handler addresses from the base of the memory map (typically the start of Flash). By writing a new address to VTOR, you redirect all interrupt dispatching to a vector table at a different location — in a different region of Flash, or even in RAM.

The most common reason to relocate the vector table is in a bootloader architecture. A bootloader occupies the first portion of Flash (e.g., 0x08000000 to 0x08003FFF) with its own vector table at the base. The application firmware starts at a higher address (e.g., 0x08004000) with its own separate vector table. When the bootloader finishes and jumps to the application, it must set VTOR to 0x08004000 so that all subsequent interrupts dispatch to the application's handlers instead of the bootloader's. Without this step, a UART interrupt in the application would vector to the bootloader's UART handler (or worse, a Default_Handler infinite loop), causing a crash or hang. The jump sequence is: set VTOR, load the application's initial MSP from its vector table entry 0, then branch to the Reset_Handler address from entry 1.

A second use case is copying the vector table to RAM for runtime ISR modification. On Cortex-M, the vector table entries in Flash are read-only (without a Flash erase/program cycle). If the application needs to dynamically install interrupt handlers at runtime — for example, a plugin system or a DMA channel that changes its completion callback — the vector table can be copied to a RAM array, VTOR pointed to the RAM copy, and then entries modified freely. This is also useful for performance: RAM access is faster than Flash on some MCUs (especially at high clock speeds without Flash accelerator), so servicing interrupts from a RAM-based vector table can reduce interrupt latency by a few cycles. The RAM array must be aligned to a power-of-two boundary that is at least the size of the table (e.g., 256-byte or 512-byte alignment), otherwise VTOR ignores the low bits and the table is misaligned.