What is "wait state"?

A wait state is one or more extra clock cycles deliberately inserted into a bus/memory access cycle to give a slow memory or peripheral enough time to respond before the CPU completes the read or write. When the processor is faster than the device it is accessing, the device (or the memory controller) holds the CPU—often via a READY/WAIT/HOLD handshake or a programmed number of wait cycles—so data is valid before it is latched. Wait states trade performance for compatibility with slower devices; this is why fast caches, prefetch, and configurable flash wait-state settings (common on modern MCUs running flash slower than the core clock) are used to minimize the penalty.