Where does the interrupt table reside in the memory map for various processor families?

The vector table (interrupt/exception table) holds the entry points the CPU jumps to on reset, faults, and interrupts. Location varies by family:

• ARMv7-M (Cortex-M3/M4/M7) and ARMv6-M (Cortex-M0/M0+): By default the vector table is at address 0x00000000, which is typically aliased to the start of flash where the image is linked. On ARMv7-M (and the Cortex-M0+, where it is an implementation option) it is relocatable via the VTOR (Vector Table Offset Register) in the System Control Block; the base Cortex-M0 (ARMv6-M) has no VTOR, so its table is fixed at address 0. This is how bootloaders work: the bootloader keeps its table low, then sets VTOR to the application's table (e.g., in flash at the app's base, or in SRAM for RAM-resident vectors). The Cortex-M table is a table of addresses (the first entry is the initial Main Stack Pointer value, the second is the reset vector), not branch instructions.
• Classic ARM (ARM7/ARM9, ARMv4/v5, A-profile legacy "exception vectors"): The exception vectors live at 0x00000000 (low vectors) or, if SCTLR.V/high-vectors is enabled, at 0xFFFF0000 (high vectors). Here the table is a set of instructions (typically branches/LDR PC, ...), one per exception type (Reset, Undefined, SWI, Prefetch Abort, Data Abort, IRQ, FIQ). Systems often remap RAM/ROM to address 0 at boot so the vectors can be patched.
• ARMv7-A / ARMv8-A (Cortex-A, application processors): Use a vector base address register — VBAR (and HVBAR/VBAR_EL1/VBAR_EL2/VBAR_EL3 for the various exception levels in AArch64). The OS/firmware programs VBAR to point at its exception vector page; there is no fixed hardware address in normal operation.
• x86 / x86-64 (real mode): The Interrupt Vector Table (IVT) is at physical 0x00000000, 256 entries × 4 bytes (segment:offset).
• x86 / x86-64 (protected/long mode): Replaced by the Interrupt Descriptor Table (IDT), located anywhere in memory; its base and limit are loaded into the IDTR via the LIDT instruction. 256 gate descriptors.
• AVR (e.g., ATmega, original Arduino): Vectors are at the start of program (flash) memory, beginning at address 0x0000 (each entry is a jump instruction). They can be moved to the boot section (for bootloaders) via the IVSEL bit in MCUCR.
• RISC-V: The trap entry address is held in the mtvec CSR (and stvec for supervisor mode). It supports direct mode (all traps go to one base address) and vectored mode (base + 4×cause for interrupts). The base is software-defined, not fixed.

Common theme: older/simple cores have a fixed low (or high) address; modern cores make the vector base programmable via a register (VTOR, VBAR, IDTR, mtvec) so multiple images (bootloader + app) and OSes can coexist.