Which endianness is: A) x86 families. B) ARM families. C) internet protocols. D) other processors? One of these is kind of a trick question.

Endianness describes the byte order used to store a multi-byte scalar in memory. Little-endian stores the least-significant byte at the lowest address; big-endian stores the most-significant byte at the lowest address.

• A) x86 / x86-64 (Intel, AMD): Little-endian. This is fixed for the architecture.
• B) ARM — this is the "trick": ARM is bi-endian (switchable). The core can operate little-endian or big-endian, selectable via a control bit (e.g., the E bit in the CPSR/SCTLR.EE on the appropriate ARM generation, controlled by the SETEND instruction on classic/A-profile cores). In practice, the overwhelming majority of real ARM systems — Cortex-M, and Linux/Android/iOS on Cortex-A — run little-endian ("ARM LE" / armel/armhf/aarch64), so people often answer "little-endian," but the architecturally correct answer is that ARM can do both. Note also that even in big-endian configurations, ARM instruction fetch and the System Control space are handled in a defined way; the data endianness is the part that is configurable.
• C) Internet / network protocols: Big-endian, a.k.a. network byte order. Protocol header fields (IP, TCP, UDP, etc.) are big-endian, which is why code uses htons()/htonl()/ntohs()/ntohl() to convert between host and network order. On a little-endian host these macros actually swap bytes; on a big-endian host they are no-ops.
• D) Other processors: Mixed.
  • Little-endian: RISC-V (LE by default, though the spec allows BE), most DSPs.
  • Big-endian (historically): Motorola 68k, classic PowerPC/Power (Power is also bi-endian in later revisions, and POWER8+ commonly runs LE), SPARC, older MIPS (MIPS is bi-endian; you see both mips BE and mipsel LE).

Key practical takeaways:

• Endianness only matters when the same memory/bytes are interpreted with different widths, or when bytes cross a boundary (files, networks, shared memory, peripheral registers, DMA buffers between dissimilar hosts).
• Within a single CPU, endianness is invisible to ordinary arithmetic; it becomes visible with type-punning (union, casting a uint8_t* over a uint32_t), serialization, and bit/byte-level protocol parsing.
• Defensive practice: serialize with explicit byte order (or use htonl/be32toh/le32toh families), never memcpy a struct over the wire and assume the other end agrees.