SPI

Quick Cap

SPI (Serial Peripheral Interface) is a synchronous, full-duplex serial communication protocol using four signals (MOSI, MISO, SCLK, CS) for high-speed data transfer between a microcontroller and peripherals. It is the fastest common embedded serial protocol, with clock rates from 1 MHz to 50+ MHz, making it the go-to choice for flash memory, ADCs, DACs, displays, and sensors that need high throughput.

Interviewers probe SPI to test whether you understand clock mode configuration (CPOL/CPHA), chip select timing for multi-slave buses, and the trade-offs between SPI vs I2C. A real-world example: a data acquisition system reading multiple 16-bit ADCs at 20 MHz while also logging to SPI flash — you need to manage per-slave clock speeds, CS timing, and DMA to sustain throughput without CPU bottlenecks.

Key Facts:

• Four-wire interface: MOSI (master out), MISO (master in), SCLK (clock), CS (chip select)
• Full-duplex communication: Simultaneous bidirectional data transfer via shift registers
• Configurable modes: Four SPI modes based on clock polarity (CPOL) and phase (CPHA)
• High-speed operation: Typically 1-50 MHz, some devices support 100+ MHz
• Multi-slave support: Dedicated chip select line per slave device
• No addressing overhead: No address bytes, ACK bits, or start/stop conditions

Deep Dive

At a Glance

Bus Interface

How SPI Works

SPI communication is based on shift registers. The master and slave each have an 8-bit (or 16/32-bit) shift register connected in a ring:

1. Master asserts CS (drives low) to select a slave
2. Master generates clock pulses on SCLK
3. On each clock edge, the master shifts one bit out on MOSI and simultaneously shifts one bit in from MISO
4. After 8 clocks, the master and slave have exchanged one byte
5. Master deasserts CS (drives high) to end the transaction

Because data flows in both directions simultaneously, SPI is inherently full-duplex. Even if you only want to read, you must clock out dummy bytes; even if you only want to write, you'll receive (and discard) bytes.

Clock Modes (CPOL / CPHA)

SPI defines four clock modes based on two parameters that control when data is sampled:

• CPOL (Clock Polarity) — idle state of the clock line (0 = low, 1 = high)
• CPHA (Clock Phase) — which clock edge data is captured on (0 = first/leading edge, 1 = second/trailing edge)

Mode 0 and Mode 3 are the most common. Both sample on the same relative clock edge — they differ only in the idle state. Most flash memory, sensors, and ADCs use Mode 0. The correct mode for a device is specified in its datasheet.

SPI Transaction: Flash Read

• CS LOW/HIGH (red) — Master asserts CS to start, deasserts to end. Only selected slave responds.
• Cmd (purple) — Command byte on MOSI (0x03 = Read). Slave receives but MISO is ignored.
• Addr (blue) — 3-byte address on MOSI. Slave still preparing, MISO ignored.
• Data (orange) — Master clocks out dummy bytes on MOSI. Slave sends data back on MISO. Full-duplex: both lines active on every clock cycle.

Chip Select (CS) Management

CS is an active-low signal. When the master drives CS low, the selected slave enables its MISO driver and responds to clock/data. When CS is high, the slave ignores the bus and its MISO goes to high-impedance (tri-state), preventing bus contention.

Why active-low? Pull-up resistors keep all CS lines high by default, so unselected slaves are naturally deselected. This also provides noise immunity — a floating line defaults to the safe (deselected) state.

Multi-slave topologies:

SPI vs I2C — When to Choose Which

Signal Integrity and Speed Limits

At high SPI clock speeds (above 10 MHz), signal integrity becomes critical:

• PCB trace length: Keep traces short. Long traces add capacitance and inductance, causing signal degradation.
• Rise/fall time: The GPIO driver must be fast enough for the clock frequency. Check the MCU's IO drive strength settings.
• Setup and hold time: The slave needs minimum time for data to be stable before and after the sampling edge. Check the slave datasheet.
• Level shifters: If master and slave run at different voltages, level shifters add propagation delay — factor this into maximum clock speed.
• Termination: At very high speeds, series termination resistors (22-33 ohm) near the master may reduce ringing.

Rule of thumb: Start with the slave's maximum rated clock speed, then reduce if you see data corruption. Use an oscilloscope to verify signal quality.

Data Transfer Methods

For high-throughput applications (continuous ADC sampling, display updates, flash read/write), DMA is essential. The CPU configures the DMA channel with source/destination addresses and transfer length, then the DMA engine handles the byte-by-byte SPI exchange without CPU intervention.

Debugging Story: The Intermittent Flash Corruption

A team was debugging intermittent data corruption when writing to SPI flash. Reads returned correct data most of the time, but occasional bytes were wrong. The SPI mode and wiring were correct. After connecting an oscilloscope, they found the issue: the CS line had a slow rise time due to a large pull-up resistor (100k), and the flash chip was occasionally interpreting the slow CS transition as a glitch, starting a new command mid-transaction. Replacing the pull-up with 10k and adding proper CS setup/hold delays fixed the issue.

Lesson: CS timing is as important as data timing. Always verify CS setup time (time between CS assertion and first clock edge) and CS hold time (time between last clock edge and CS deassertion) against the slave datasheet.

What interviewers want to hear: You understand SPI mode configuration (CPOL/CPHA) and can explain when to use each, you know how chip select timing affects multi-slave reliability, you can reason about throughput vs CPU/DMA trade-offs, and you understand the signal integrity challenges at high clock speeds.

Interview Focus

Classic SPI Interview Questions

Q1: "What are CPOL and CPHA, and how do the four SPI modes differ?"

Model Answer Starter: "CPOL defines the clock idle state and CPHA defines which edge data is sampled on. Mode 0 (CPOL=0, CPHA=0) samples on the rising edge with clock idle low — this is the most common mode for sensors and flash. Mode 3 (CPOL=1, CPHA=1) also samples on the rising edge but with clock idle high. Both master and slave must use the same mode, which is specified in the slave's datasheet."

Q2: "How do you handle SPI communication with multiple slaves?"

Model Answer Starter: "Each slave gets a dedicated CS line controlled by GPIO. I assert only one CS at a time to prevent bus contention on MISO. Each slave may need different SPI mode and clock speed settings, so I reconfigure the SPI peripheral before each transaction if needed. For systems with many slaves, I use a decoder IC to expand GPIO pins. Proper CS timing — setup time before the first clock edge and hold time after the last — is critical for reliable operation."

Q3: "SPI has no built-in error detection. How do you ensure data integrity?"

Model Answer Starter: "I add CRC at the application protocol level. For flash writes, I read back and verify. Many SPI devices have status registers I can poll to confirm operations completed successfully. For critical data, I implement a command-response protocol with checksums. At the hardware level, I keep traces short, use proper decoupling, and verify signal quality with an oscilloscope when debugging."

Q4: "When would you choose SPI over I2C?"

Model Answer Starter: "SPI when I need high throughput — flash memory, ADC streaming, display driving — because SPI runs at 10-50 MHz vs I2C's 400 kHz - 3.4 MHz. Also when I need full-duplex or when the device only supports SPI. I2C when I have many low-speed devices and limited pins, since I2C only needs 2 wires regardless of device count. The choice is usually dictated by the peripheral's available interfaces."

Trap Alerts

• Don't say: "SPI is just serial communication" — it has specific mode and timing requirements
• Don't forget: CS timing requirements and the risk of bus contention with multiple slaves
• Don't ignore: Signal integrity at high frequencies and the lack of built-in error detection

Follow-up Questions

• "How would you implement SPI communication with devices that have different speed requirements?"
• "What's your strategy for SPI bus recovery when a slave device malfunctions?"
• "How does SPI daisy-chaining work and when would you use it?"

Practice

Real-World Tie-In

High-Speed Data Acquisition System

In the field, I worked on a data acquisition system interfacing with multiple 16-bit ADCs, SPI flash for storage, and an RTC module — all on one SPI bus. Each device had different speed and mode requirements: the ADCs ran at 20 MHz in Mode 0, the flash at 50 MHz in Mode 0, and the RTC at 1 MHz in Mode 3. I used per-device SPI reconfiguration before each transaction, DMA for the ADC stream to avoid CPU bottlenecks, and careful CS timing to meet each device's setup/hold requirements. The system sustained 80 Mbps aggregate throughput with 99.99% data integrity.

Industrial Motor Controller

On the job, we designed a motor controller using SPI to communicate with a high-resolution encoder, a DAC for current control, and flash for parameter storage in an electrically noisy factory environment. Signal integrity was critical — we used short traces, series termination resistors, and proper grounding. The encoder required Mode 1 while the DAC used Mode 0, so the driver reconfigured the SPI peripheral on each CS switch. By implementing DMA double-buffering and careful CS timing, the system achieved deterministic 100 us control loop updates.