Explain cache coherency issues with DMA and how to solve them.

Cache coherency problems arise because the DMA controller and the CPU access main SRAM through different paths. The CPU reads and writes through the data cache (D-Cache), which keeps a local copy of recently accessed memory. The DMA controller bypasses the cache entirely — it reads from and writes to main SRAM directly via the bus matrix. This creates two distinct problems depending on the data flow direction.

DMA RX (DMA writes, CPU reads): The DMA deposits fresh data — ADC samples, UART bytes, SPI responses — into a RAM buffer. But the CPU's D-Cache may still hold stale copies of those same addresses from a previous access. When the CPU reads the buffer after the DMA transfer completes, it gets the old cached values, not the new DMA data. The symptom is maddening: your ADC buffer shows the same readings repeatedly, or UART RX data appears frozen. Everything works perfectly on Cortex-M4 (which has no cache) and breaks on M7. Solution: Call SCB_InvalidateDCache_by_Addr() on the buffer after the DMA transfer completes. This discards the stale cache lines, forcing the CPU to fetch fresh data from SRAM on the next read.

DMA TX (CPU writes, DMA reads): The CPU fills a transmit buffer, but the writes may be sitting in the cache's dirty lines and have not been flushed to main SRAM. When DMA reads the buffer to feed the peripheral, it reads stale SRAM contents — potentially garbage from a previous transfer or uninitialized memory. Solution: Call SCB_CleanDCache_by_Addr() before starting the DMA transfer, which pushes dirty cache lines out to SRAM. Alternative solutions include: marking the buffer's memory region as non-cacheable via the MPU (simple but sacrifices cache performance for all CPU accesses to that region), or placing DMA buffers in DTCM/TCM, which is not cached and provides single-cycle access. Critical requirement: DMA buffers must be cache-line aligned (32 bytes on M7) and sized as multiples of 32 bytes, because cache operations work on whole cache lines.