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MCU & System Architecture
CPU Fundamentals
CPU Fundamentals Interview Questions
10 questions in
MCU & System Architecture
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Explain cache coherency issues with DMA and how to solve them.
CPU Fundamentals
Cache & DMA Coherency
foundational
0
Write-through vs write-back cache — tradeoffs in embedded?
CPU Fundamentals
Cache & DMA Coherency
foundational
0
How do you ensure a DMA buffer is cache-line aligned and why does it matter?
CPU Fundamentals
Cache & DMA Coherency
foundational
#4
0
Why does pipeline flush matter for interrupt latency?
CPU Fundamentals
Pipeline & Barriers
foundational
#5
0
What are memory barriers (DSB, DMB, ISB) and when do you need them?
CPU Fundamentals
Pipeline & Barriers
foundational
#6
0
You enable a peripheral clock and immediately write to its registers. What could go wrong?
CPU Fundamentals
Pipeline & Barriers
foundational
#7
0
What is the difference between AHB and APB buses?
CPU Fundamentals
Bus Architecture & Memory Types
foundational
#8
0
What is TCM and when would you use it instead of regular SRAM?
CPU Fundamentals
Bus Architecture & Memory Types
foundational
#9
0
What is the difference between Flash, SRAM, TCM, and CCM on Cortex-M7?
CPU Fundamentals
Bus Architecture & Memory Types
foundational
#10
0
Little-endian vs big-endian — when does it matter in embedded?
CPU Fundamentals
Bus Architecture & Memory Types
foundational
