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MCU & System Architecture
Interrupts & Priorities
Interrupts & Priorities Interview Questions
12 questions in
MCU & System Architecture
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What happens step by step when an interrupt fires on a Cortex-M processor?
Interrupts & Priorities
ISR Design & Basics
foundational
0
Why should ISRs be kept short? What do you do if an interrupt requires heavy processing?
Interrupts & Priorities
ISR Design & Basics
foundational
0
What are the rules for writing a safe ISR? What mistakes do you commonly see?
Interrupts & Priorities
ISR Design & Basics
foundational
#4
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Explain preemption priority vs sub-priority on the NVIC. How does PRIGROUP configure them?
Interrupts & Priorities
Priority & Nesting
foundational
#5
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What is tail-chaining and how does it improve interrupt throughput?
Interrupts & Priorities
Priority & Nesting
foundational
#6
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How does interrupt nesting work on Cortex-M? What are the stack implications?
Interrupts & Priorities
Priority & Nesting
foundational
#7
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How do you safely share data between an ISR and the main loop?
Interrupts & Priorities
Shared Data Protection
foundational
#8
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What is a critical section and how do you implement one on Cortex-M?
Interrupts & Priorities
Shared Data Protection
foundational
#9
0
What are the risks of calling printf from an ISR?
Interrupts & Priorities
Shared Data Protection
foundational
#10
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What causes interrupt latency and how do you minimize it?
Interrupts & Priorities
Latency & Debugging
foundational
#11
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What is the difference between edge-triggered and level-triggered interrupts? When does each matter?
Interrupts & Priorities
Latency & Debugging
foundational
#12
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How would you debug a system where interrupts seem to be lost or not firing?
Interrupts & Priorities
Latency & Debugging
foundational
