What happens step by step when an interrupt fires on a Cortex-M processor?

When an interrupt request is asserted and its priority is higher than the current execution priority, the Cortex-M hardware initiates an automatic exception entry sequence. First, the processor finishes the currently executing instruction — it never aborts mid-instruction, so worst-case latency depends on the longest instruction (an LDM/STM of multiple registers can take many cycles). Then the hardware automatically pushes eight registers onto the current stack (MSP or PSP): R0-R3, R12, LR, PC (the return address), and xPSR. This "stacking" happens in parallel with the vector table lookup, which is a key Cortex-M optimization — the processor fetches the ISR address from the vector table (at offset 0x00000000 + 4 * IRQ_number) simultaneously with the register save, reducing entry latency. On Cortex-M3/M4, this takes 12 cycles from interrupt assertion to first ISR instruction.

Once stacking is complete and the vector is fetched, the processor transitions to Handler mode, updates the link register with a special EXC_RETURN value (e.g., 0xFFFFFFF9 for return to MSP thread mode), and begins executing the ISR. The ISR runs at the priority of the interrupt, meaning only higher-priority interrupts can preempt it. When the ISR returns (via BX LR with the EXC_RETURN value), the hardware automatically pops the eight stacked registers ("unstacking"), restores the processor state, and resumes the interrupted code. The entire save/restore mechanism is done in hardware with zero compiler cooperation, which is why Cortex-M ISRs are ordinary C functions — no special prologue/epilogue or __interrupt keywords needed.

A common interview trap is forgetting the parallel stacking and vector fetch. Candidates who describe them as sequential steps overestimate the entry latency. Another subtlety: if a higher-priority interrupt arrives during stacking, the processor completes the stack frame but redirects to the higher-priority ISR instead — the original pending interrupt is serviced after the higher one returns, with tail-chaining eliminating redundant stack operations.