What is TCM and when would you use it instead of regular SRAM?

TCM (Tightly Coupled Memory) is a dedicated SRAM connected directly to the CPU core through a private bus, bypassing the main bus matrix and cache entirely. On Cortex-M7, there are two types: ITCM (Instruction TCM) for code and DTCM (Data TCM) for data. The defining characteristic is zero wait-state, deterministic access — every read and write completes in exactly one clock cycle, regardless of what the DMA, other bus masters, or the cache are doing.

This determinism makes TCM ideal for interrupt service routines and real-time control loops. When an ISR is in ITCM, the instruction fetch latency is always one cycle — no cache misses, no flash wait states, no bus contention from concurrent DMA transfers. When the ISR's data (lookup tables, filter coefficients, control state) is in DTCM, every load and store is also one cycle. This eliminates the timing variability that makes worst-case execution time (WCET) analysis so difficult with cached memory.

Specific use cases include: (1) DMA descriptors and small DMA buffers — DTCM is not cached, so there are no cache coherency issues with DMA. Placing DMA buffers in DTCM eliminates the need for cache maintenance calls entirely. (2) Stack memory — placing the main stack (MSP) in DTCM ensures that context save/restore during ISR entry has deterministic timing. (3) High-frequency ISR code — a motor FOC (Field-Oriented Control) ISR running at 20 kHz with hard real-time deadlines benefits from ITCM placement because cache misses on the first invocation after a context switch are eliminated. (4) Audio processing buffers — real-time audio codecs that cannot tolerate jitter from cache misses or bus contention.

The limitation is size: TCM is typically 64-128 KB on STM32H7, shared among all these use cases. You cannot put everything in TCM, so you must profile your application to identify the code and data that benefit most from deterministic access and place only those items in TCM via linker script sections.