What is the difference between AHB and APB buses?

ARM Cortex-M microcontrollers use a multi-layer bus architecture based on the AMBA (Advanced Microcontroller Bus Architecture) specification. The two primary buses — AHB (Advanced High-performance Bus) and APB (Advanced Peripheral Bus) — serve different classes of peripherals and operate at different speeds.

AHB runs at the full system clock frequency (SYSCLK) and connects high-bandwidth peripherals: SRAM, Flash memory interface, DMA controllers, GPIO ports, and the bus matrix itself. AHB supports pipelined, burst, and split transactions, enabling high throughput. A GPIO write on AHB completes in a single clock cycle — critical for bit-banging protocols or toggling pins at the maximum possible rate. AHB is also where the CPU's instruction and data buses connect, so all code and data fetches go through AHB.

APB is connected to AHB through a bridge (AHB-to-APB bridge) and runs at a prescaled fraction of SYSCLK — typically SYSCLK/2 or SYSCLK/4. It connects lower-bandwidth peripherals: UART, SPI, I2C, timers, ADC, DAC, and RTC. APB uses a simpler protocol with no burst support, reducing gate count and power consumption for peripherals that do not need high bandwidth. The trade-off is access latency: an APB register read takes 2-3 system clock cycles because of the bridge synchronization — the AHB-to-APB bridge must synchronize the request across clock domains and relay the response back.

This distinction matters for firmware optimization. If you are polling an APB peripheral's status register in a tight loop, each read costs 2-3 cycles instead of 1. For GPIO-heavy operations (bit-banging, LED matrix driving), STM32 places GPIO on AHB specifically to enable single-cycle access. When calculating peripheral clock rates for baud rate generators or timer prescalers, remember that APB peripherals are clocked at the APB bus frequency (PCLK1 or PCLK2), not SYSCLK — a common source of baud rate errors when configuring UART or SPI.